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Giant-scale patterning for vapor-liquid-solid progress of III-V nanowires is a problem given the required function dimension for patterning (45 to 60nm holes). In actual fact, arrays are historically manufactured utilizing electron-beam lithography, for which processing instances improve significantly when increasing the publicity space. To be able to carry nanowire arrays one step nearer to the wafer-scale we take a unique method and exchange patterned holes with Si pillars which might be between 150nm to 200nm in dimension. We fabricate them utilizing photolithography strategies resembling phase-shift lithography or deep ultraviolet (DUV) stepper lithography. We use Si oxidation to succeed in the specified function sizes and stabilize the Ga catalyst droplet with the intention to efficiently develop nanowire arrays. On this research we first determine the important thing parameters and basic features of nanowire progress on Si pillars by electron-beam lithography, the place we attain vertical yields of 55%. We present that the droplet configuration, i.e contact angle and triple section line, are central for a profitable progress, and that the pillar geometry permits to engineer the droplet contact angle. We examine our experiments with simulations carried out in floor evolver(tm) and observe a powerful correlation. We then manufacture SiO2/Si pillars utilizing phase-shift lithography and develop large-area GaAs nanowire arrays. We attain a most native vertical yield of 67% and a world chip-scale yield of 40%. We imagine that, by means of a better management over sure key processing steps, resembling reactive ion etching, one can push this yield to 90+% and open views for deterministic nanowire phase-engineering on the wafer-scale.
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