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Codasip has launched two new RISC-V processor cores, the L11 and L31, which it claims are ideally suited to use in supply edge AI by way of tinyML — because of the corporate’s first official assist for TensorFlow Lite for Microcontrollers.
Slotting into the corporate’s 1-Sequence and 3-Sequence households of low-power embedded processor cores, as replacements for the L10 and L30, which now stand as obtainable however “not really useful for brand new designs,” the brand new L11 and L31 cores are three-stage implementations of the free and open-source RISC-V instruction set structure.
The L11 makes use of the RV32EMC instruction set, whereas the L31 opts for RV32IMC — which means each have integer multiplication and division and compressed instruction assist, however the L11 has simply 16 registers and a sequential multiplier to the L31’s 32 register and parallel multiplier.
Codasip’s new L11 and L31 RISC-V cores embody TFLite for Microcontroller assist with optionally available customized directions. (📷: Codasip)
The largest change from the L10 and L30: The introduction of official assist for TensorFlow Lite for Microcontrollers, permitting the resource-constrained embedded cores to run machine studying workloads on the edge. On the identical time, the corporate is encouraging anybody licensing the cores so as to add customized directions for particular duties — releasing a white paper demonstrating how including simply two directions to the L31 can enhance performance-power-area (PPA) for picture classification by as much as 10 per cent.
“Licensing the CodAL description of a RISC-V core provides Codasip clients a full structure license enabling each the ISA and microarchitecture to be personalized,” explains Codasip’s chief technical officer Zdeněk Přikry. “The brand new L11/31 cores make it even simpler so as to add options our clients have been asking for, resembling edge AI, into the smallest, lowest energy embedded processor designs.”
The corporate’s software program makes it simple so as to add customized directions to a core. (📷: Codasip)
Whereas the L11 and L31 are the primary in Codasip’s RISC-V vary to assist TensorFlow Lite for Microcontrollers, they are not going to be the final: The corporate has confirmed plans so as to add assist “throughout Codasip’s whole portfolio of RISC-V cores” — however didn’t present a timescale.
events can learn extra about Codasip’s cores, and entry the white paper, on the corporate’s web site; these seeking to check out any of the cores can request an analysis equipment, which features a Digilent Nexys A7 FPGA board for testing.
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